Interactive reference for x86-64, ARM AArch64, and RISC-V instructions.
Feb 26, 2026, Eric
Adds source operand to destination operand, storing the result in the destination.
Subtracts source operand from destination operand, storing the result in the destination.
Performs signed multiplication. Two-operand form stores in dest; three-operand form multiplies src by immediate into dest.
Divides RDX:RAX by the operand. Quotient in RAX, remainder in RDX.
Increments the operand by one. Does not affect CF.
Performs bitwise AND between source and destination, storing result in destination.
Performs bitwise OR between source and destination, storing result in destination.
Performs bitwise XOR. Commonly used to zero a register (XOR RAX, RAX).
Shifts bits left by count positions, filling with zeros. Equivalent to multiply by 2^count.
Transfers control unconditionally to the target address. Can be near, short, or far.
Jumps to target if ZF=1 (last comparison was equal). Alias: JZ.
Pushes return address onto the stack and jumps to the target procedure.
Pops return address from stack and transfers control there. Optional immediate adjusts stack.
Decrements RSP by 8 and stores the source operand at [RSP].
Loads the value at [RSP] into the destination and increments RSP by 8.
Computes the effective address of the source and stores it in destination. Does not access memory.
Copies the source operand to the destination. The most common x86 instruction.
Copies a smaller source operand into a larger destination, filling upper bits with zeros.
Atomically swaps the values of two operands. Implicit LOCK prefix when a memory operand is used.
Subtracts op2 from op1 without storing the result. Sets flags for conditional jumps.
Performs bitwise AND without storing the result. Often used to check if a register is zero.
Fast system call entry to the kernel. RAX holds the syscall number; args in RDI, RSI, RDX, R10, R8, R9.
Does nothing. Used for alignment, padding, and timing. Multi-byte NOP forms exist.
Adds the low single-precision float in source to destination. Upper elements unchanged.
Multiplies four packed single-precision floats in parallel (SIMD).
Adds operand2 to Xn and writes the result to Xd. operand2 can be an immediate or shifted register.
Subtracts operand2 from Xn and writes the result to Xd.
Multiplies Xn by Xm, adds Xa, and writes to Xd. MUL is an alias with XZR as Xa.
Signed integer division of Xn by Xm, storing the quotient in Xd. No remainder — use MSUB to compute it.
Negates Xm and writes to Xd. Alias for SUB Xd, XZR, Xm.
Performs bitwise AND of Xn and operand2, result in Xd.
Performs bitwise OR of Xn and operand2, result in Xd.
Performs bitwise XOR of Xn and operand2, result in Xd.
Shifts Xn left by the specified amount. Alias for UBFM/LSLV.
Unconditional branch to a PC-relative label within +/-128 MB range.
Branches to label if the Z flag is set (last comparison was equal).
Stores return address in X30 (LR) and branches to label. Used for function calls.
Branches to the address in Xn (defaults to X30/LR). Standard function return.
Loads a 64-bit value from memory at base+offset into Xt. Supports pre/post-indexing.
Stores the 64-bit value in Xt to memory at base+offset.
Loads two 64-bit values from consecutive memory into two registers. Common for function prologue/epilogue.
Copies a value into Xd. Alias for ORR Xd, XZR, operand2 or MOVZ/MOVK for wide immediates.
Writes a 16-bit immediate into a 16-bit slice of Xd, keeping all other bits unchanged. Used to build large constants.
Subtracts operand2 from Xn, discards the result, and sets the condition flags. Alias for SUBS XZR.
Performs bitwise AND of Xn and operand2, discards the result, and sets flags. Alias for ANDS XZR.
If cond is true, Xd = Xn; otherwise Xd = Xm. Branchless conditional move.
Generates a supervisor call exception to request an OS service. The syscall number is in X8.
Does nothing. Fixed 4-byte encoding. Used for alignment and instruction stream padding.
Adds floating-point values. Scalar form operates on D/S registers; vector form on V registers with arrangement specifier.
Multiplies floating-point values. Vector form multiplies packed elements in parallel.
Adds rs1 and rs2, storing the result in rd. No flags are set.
Adds a sign-extended 12-bit immediate to rs1, storing in rd. The most common RISC-V instruction.
Subtracts rs2 from rs1, storing the result in rd.
Multiplies rs1 by rs2, storing the lower XLEN bits in rd. Part of the M extension.
Signed integer division of rs1 by rs2. Result is the quotient. Part of the M extension.
Performs bitwise AND of rs1 and rs2, storing result in rd.
Performs bitwise OR of rs1 and rs2, storing result in rd.
Performs bitwise XOR of rs1 and rs2, storing result in rd.
Shifts rs1 left by shamt bits, filling with zeros.
Stores PC+4 in rd and jumps to PC+offset. Used for function calls (rd=ra) and unconditional jumps (rd=x0).
Stores PC+4 in rd and jumps to (rs1+offset)&~1. Used for indirect calls and returns.
Branches to PC+offset if rs1 equals rs2. No flags — comparison is built into the branch.
Branches to PC+offset if rs1 < rs2 (signed comparison).
Loads a 64-bit value from memory at rs1+offset into rd. RV64I instruction.
Stores the 64-bit value in rs2 to memory at rs1+offset.
Loads a 32-bit value from memory, sign-extending it to 64 bits in RV64.
Loads a 20-bit immediate into bits [31:12] of rd, zeroing bits [11:0]. Used with ADDI to build 32-bit constants.
Adds a 20-bit upper immediate to PC and stores in rd. Foundation for PC-relative addressing.
Sets rd to 1 if rs1 < rs2 (signed), else 0. RISC-V uses this instead of flag registers.
Sets rd to 1 if rs1 < rs2 (unsigned), else 0. SLTU rd, x0, rs2 sets rd to 1 if rs2 is nonzero (SNEZ pseudo).
Sets rd to 1 if rs1 < sign-extended immediate (signed), else 0.
Generates an environment call exception. Used to make system calls. Syscall number in a7, args in a0-a5.
Orders memory operations. Ensures all memory ops of predecessor type complete before successor type begins.
Adds single-precision floats in rs1 and rs2, storing result in rd. Part of the F extension.
Multiplies single-precision floats in rs1 and rs2. Part of the F extension.